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tmp86fm29 2004-03-01 difference comparison table of tmp86c829b/h29b/m29b/pm29a/pm29b/c929axb and tmp86fm29 tmp86c829b tmp86ch29b TMP86CM29B tmp86pm29a tmp86pm29b tmp86c929axb (emulation chip) (note 3) tmp86fm29f rom 8 k (mask rom) 16 k (mask rom) 32 k (mask rom) 32 k (otp) ? 32 k (flash) ram 512 1.5 k 1.5 k 1.5 k ? 2 k i/o 42 pin 42 pin (mcu part) 42 pin external interrupt 5 pin 5 pin ad converter 10-bit ad converter 8 ch 10-bit ad converter 8 ch timer counter 18-bit timer 1 ch 8-bit timer 4 ch 18-bit timer 1 ch 8-bit timer 4 ch serial interface 8-bit uart / sio 1 ch 8-bit uart / sio 1 ch lcd 32 seg 4 com 32 seg 4 com (note 2) key-on wakeup 4 ch 4 ch operating voltage in mcu mode 1.8 to 5.5 v at 4.2 mhz 2.7 to 5.5 v at 8 mhz 4.5 to 5.5 v at 16 mhz 1.8 to 5.25 v at 4.2 mhz 2.7 to 5.25 v at 8 mhz 4.5 to 5.25 v at 16 mhz 1.8 to 3.6 v at 4.2 mhz (external clock) 1.8 to 3.6 v at 8 mhz (resonator) 2.7 to 3.6 v at 16 mhz operating temperature in mcu mode ? 40 to 85 0 to 60c ? 40 to 85c writing to flash memory ? 2.7 to 3.6v at 16 mhz 25c 5c cpu wait (note 1) n/a available note 1: the cpu wait is a cpu halt function for stabilizing of power supply of flash memory. the cpu wait period is as follows. in the cpu wait period except reset, cpu is halted but peripheral functions are not halted. therefore, if the interrupt occurs during the cpu wait period, the interrupt latch is set. in this case, if the imf has been set to ?1?, the interrupt service routine is executed after cpu wait period. for details refer to 2.14 ?flash memory? in tmp86fm29 data sheet. thus, even if the same software is executed in 86fm29 and 86c829b/h29b/m29b/pm29a/pm29b /c929axb, the operation process is not the same. therefore, when the final operating confirmation on target application is executed for software development of mask rom product (86c829b/h29b/m29b), not the flash product (86fm29) but the otp product (86pm29a/pm29b) should be used. halt/operate condition wait time cpu peripherals after reset release 2 10 /fc[s] halt halt changing from stop mode to normal mode (at eepcr = ?1?) 2 10 /fc[s] halt operate changing from stop mode to slow mode (at eepcr = ?1?) 2 3 /fs[s] halt operate changing from idle0/1/2 mode to normal mode (at eepcr = ?0?) 2 10 /fc[s] halt operate changing from sleep0/1/2 mode to slow mode (at eepcr = ?0?) 2 3 /fs[s] halt operate
tmp86fm29 2004-03-01 note 2: the 86fm29 can not drive the 5v lcd panel because the electrical characteristics in 86fm29 is altered from 86c829b/h29b/m29b/pm29a/pm29b/c929axb. the recommended operating condition of v3 pin in tmp86fm29 is 3.6v(max). for details, refer to ?electrical characteristics?. when the lcd booster circuit is used in 86fm29, connect the reference voltage and capacitor as shown in "case2". though the method of "case1" has been recommended in 86c829b /h29b/m29b/pm29a/pm29b datasheets, the 86fm29 should not use method of "case1". even if the method of "case1" is used in the 86c829b/h29b/m29b/pm29a/pm29b/c929axb, the function and operation are not issue at all. however, if the "case2" is used, the booster ability becomes higher than "case1". therefore, when the application board is designed newly in future, the method of "case2" is also recommended in 86c829b/h29b/m29b/pm29a/pm29b/c929axb. note 3: flash function, cpu wait period and serial prom mode cannot be emulated in the 86c929axb. if the software including the flash function is executed in 86c929axb, the operation process differs from 86fm29. vdd vss v3 v2 v1 c1 c0 c c c reference voltage (1 v) vdd vss v3 v2 c0 c1 v1 c reference voltage (1 v) c c case 1 (for 86c829b/h29b/m29b/pm29a/pm29b/c929axb) case 2 (for 86fm29 and 86c829b/h29b/m29b/ pm29a/pm29b/c929axb)
tmp86fm29 2004-03-01 86fm29-1 cmos 8-bit microcontroller tmp86fm29ug/fg the tmp86fm29 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including flash, ram, lcd driver, multi-function timer/counter, serial interface (uart/sio), a 10-bit ad converter and two clock generators on chip. product no. flash ram package emulation chip tmp86fm29ug p-lqfp64-1010-0.50e tmp86fm29fg 32768 8 bits 1536 8 bits p-qfp64-1414-0.80c tmp86c929axb feautures ? 8-bit single chip microcomputer tlcs-870/c series ? instruction execution time: 0.25 s (at 16 mhz) 122 s (at 32.768 khz) ? 132 types and 731 basic instructions ? 19 interrupt sources (external: 5, internal: 14) ? input/output ports (39 pins) (out of which 24 pins are also used as seg pins) ? 18-bit timer counter: 1 ch ? timer, event counter, pulse width measurement, frequencymeasurement modes ? 8-bit timer counter: 4 ch ? timer, event counter, pwm output, programmable divider output, ppg output modes ? time base timer ? divider output function p-qfp64-1414-0.80c p-lqfp64-1010-0.50e tmp86fm29ug tmp86fm29fg ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is gran ted b y implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury o r damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion con trol instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstream products which are prohibited to be produced and sold, under an y law and regulations. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitl ed qualit y and reliability assurance/handling precautions. 030619 ebp1
tmp86fm29 2004-03-01 86fm29-2 ? watchdog timer ? interrupt source/reset output (programmable) ? serial interface ? 8-bit uart/sio: 1ch ? 10-bit successive approximation type ad converter ? analog input: 8 ch ? four key-on wake-up pins ? lcd driver/controller ? built-in voltage booster for lcd driver ? with displaymemory ? lcd direct drive capability (max 32 seg 4 com) ? 1/4, 1/3, 1/2duties or static drive are programmably selectable ? dual clock operation ? single/dual-clock mode ? nine power saving operating modes ? stop mode : oscillation stops. battery/capacitor back-up. port output hold/high-impedance. ? slow 1, 2 mode : low power consumption operation using low-frequency clock (32.768 khz) ? idle 0 mode : cpu stops, and peripherals operate using high-frequency clock of time-base-timer. release by falling edge of tbtcr < tbtck > setting. ? idle 1 mode : cpu stops, and peripherals operate using high-frequency clock. release by interruputs. ? idle 2 mode : cpu stops, and peripherals operate using high and low frequency clock. release by interruputs. ? sleep 0 mode : cpu stops, and peripherals operate using low-frequency clock of time-base-timer. release by falling edge of tbtcr < tbtck > setting. ? sleep 1 mode : cpu stops, and peripherals operate using low-frequency clock. release by interrupts. ? sleep 2 mode : cpu stops, and peripherals operate using high and low frequency clock. release by interrupts. ? wide operating voltage: 1.8 to 3.6 v at 8 mhz/32.768 khz 2.7 to 3.6 v at 16 mhz/32.768 khz
tmp86fm29 2004-03-01 86fm29-3 pin assignments (top view) p-lqfp64-1010-0.50e p-qfp64-1414-0.80c 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 seg2 seg1 seg0 com3 com2 com1 com0 v3 v2 v1 c1 c0 ( dvo ) p30 ( pwm3 / pdo3 /tc3) p31 ( pwm4 / pdo4 / ppg4 /tc4) p32 ( pwm6 / pdo6 / ppg6 /tc6) p33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg3 seg4 seg5 seg6 seg7 p77 (seg8) p76 (seg9) p75 (seg10) p74 (seg11) p73 (seg12) p72 (seg13) p71 (seg14) p70 (seg15) p57 (seg16) p56 (seg17) p55 (seg18) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p54 (seg19) p53 (seg20) p52 (seg21) p51 (seg22) p50 (seg23) p17 (seg24/ sck ) p16 (seg25/txd/so) p15 (seg26/rxd/si/boot) p14 (seg27/int3) p13 (seg28/int2) p12 (seg29/int1) p11 (seg30) p10 (seg31) a vdd varef p67 (ain7/stop5) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss xin xout test vdd (xtin) p21 (xtout) p22 ( / ) p20 (ain0) p60 (ain1/ecin) p61 (ain2/ecnt) p62 (ain3/int0) p63 (ain4/stop2) p64 (ain5/stop3) p65 (ain6/stop4) p66 reset int5 stop
tmp86fm29 2004-03-01 86fm29-4 block diagram xin xout power supply resonator connecting pins i/o port (segment output) vdd vss p7 address/data bus system control circuit standby control circuit (key-on wake-up) timing generator high frequency low frequency clock generator tlcs-870/c cpu data memory (ram) program memory ram interrupt controller i/o ports analog reference pins i/o ports avdd varef p67 (ain7) p60 (ain0) p77 (seg8) to p70 ( seg15 ) p2 10-bit ad converter p6 p3 uart/sio sio uart address/data bus to common outputs com3 to com0 lcd driver circuit segment outputs seg7 to seg0 p5 p57 (seg16) to p50 ( seg23 ) p1 p17 (seg24) to p10 ( seg31 ) lcd voltage booster circuit lcd power supply c0 c1 v1 v2 v3 reset i/o reset test pin test tc3 8-bit timer/counter tc4 tc5 tc6 tc1 18-bit timer/counter time base timer watchdog timer p33 to p30 p22 to p20
tmp86fm29 2004-03-01 86fm29-5 pin functions pin name input/output functions p17 (seg24, sck ) i/o (i/o) serial clock input/output p16 (seg25, txd, so) i/o (output) uart data output serial data output p15 (seg26, rxd, si boot) i/o (i/o) uart data input serial data input serial prom mode control input p14 (seg27, int3) i/o (i/o) external interrupt 3 input p13 (seg28, int2) i/o (i/o) external interrupt 2 input p12 (seg29, int1) i/o (i/o) external interrupt 1 input p11 (seg30) i/o (output) p10 (seg31) i/o (output) 8-bit input/output port with latch. when used as input port, an external interrupt input, serial interface input/output and uart data input/output, the p1lcr must be set to ?0? after setting output latch to ?1?. when used as a lcd segment output, the p1lcr must be set to ?1?. lcd segment outputs. p22 (xtout) i/o (output) p21 (xtin) i/o (input) resonator connecting pins (32.768 khz) for inputting external clock, xtin is used and xout is opened. p20 ( int5 , stop ) i/o (input) 3-bit input/output port with latch. when used as an input port, the output latch must be set to ?1?. external interrupt input 5 or stop mode release signal input p33 ( pwm6 , pdo6 ppg6 , tc6) i/o (i/o) timer counter 6 input/output p32 ( pwm4 , pdo4 ppg4 , tc4) i/o (i/o) timer counter 4 input/output p31 ( pwm3 , pdo3 , tc3) i/o (i/o) timer counter 3 input/output p30 ( dvo ) i/o (output) 4-bit programmable input/output port (nch high current output). when used as a timer/counter output or divider output, the output latch must be set to ?1?. when used as an input port or timer/counter input, the p3outcr must be set to ?0? after p3dr is set to ?1?. divider output p57 (seg16) to p50 (seg23) i/o (output) 8-bit input/output port with latch. when used as a lcd segment output, the p5lcr must be set to ?1?. lcd segment outputs p67 (ain7, stop5) i/o (input) stop 5 input p66 (ain6, stop4) i/o (input) stop 4 input p65 (ain5, stop3) i/o (input) stop 3 input p64 (ain4, stop2) i/o (input) stop 2 input p63 (ain3, int0 ) i/o (input) external interrupt 0 input p62 (ain2, ecnt) i/o (input) p61 (ain1, ecin) i/o (input) timer/counter 1 input p60 (ain0) i/o (input) 8-bit programmable input/output port (tri-state). each bit of this port can be individually configured as an input or an output under software control. when used as an analog input, the p6cr must be set to ?0? after setting output latch to ?0?. when used as an input port, a key on wake up input, an external interrupt input and timer/ counter input, the p6cr must be set to ?0? after setting output latch to ?1?. ad converter analog inputs p77 (seg8) to p70 (seg15) i/o (output) 8-bit input/output port with latch. when used as a lcd segment output, the p7lcr must be set to ?1?. lcd segment outputs seg7 to seg0 lcd segment outputs com3 to com0 output lcd common outputs v3 to v1 c1 to c0 lcd voltage booster pin lcd voltage booster pin. capacitors are required between c0 and c1 pin and v1/v2/v3 pin and gnd. xin, xout input output resonator connecting pins for high-frequency clock. for inputting external clock, xin is used and xout is opened. reset i/o reset signal input or watchdog timer output/address-trap-reset output/system clock reset output test input test pin for out-going test, and the serial prom mode control pin. usually be fixed to low level. when the serial prom mode starts, be fixed to "1". vdd, vss + 5 v, 0 (gnd) varef analog reference voltage inputs (high) avdd power supply ad circuit power supply
tmp86fm29 2004-03-01 86fm29-6 operational description 1. cpu core functions the cpu core consists of a cpu, a system clock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 memory address map the tmp86fm29 memory consists of 5 blocks: flash memory, boot rom, ram, dbr (data buffer register) and sfr (special function register). they are all mapped in 64-kbyte address space. figure 1.1.1 shows the tmp86fm29 memory address map. the general-purpose registers are not assigned to the ram address space. figure 1.1.1 memory address maps 1.2 program memory (flash) the tmp86fm29 has a 32 k 8 bits (address 8000 h to ffff h ) of flash memory. flash memory: flash memory includes: flash memory vector table boot rom: flash writing program ram: random access memory includes: data memory stack sfr: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers interrupt control registers program status word dbr: data buffer register includes: peripheral control registers peripheral status registers vector table for vector call instructions (16 vectors) vector table for interrupts/rese t (16 vectors) vector table for interrupts (8 vectors) 0000 h 64 bytes 1536 bytes 128 bytes sfr ram dbr flash memory 32688 bytes 32 bytes 32 b y tes 003f h 0040 h 063f h 0f80 h 0fff h 8000 h ffbf h ffc0 h ffdf h ffe0 h ffff h 16 bytes ffb0 h 2048 bytes boot rom 3800 h 3fff h
tmp86fm29 2004-03-01 86fm29-174 electrical characteristics absolute maximum ratings (v ss = 0 v) parameter symbol pins rating unit v dd ? 0.3 to 4.0 supply voltage v lcd v3 pin ? 0.3 to 4.0 input voltage v in ? 0.3 to v dd + 0.3 output voltage v out1 ? 0.3 to v dd + 0.3 v i out1 p3, p6 ports ? 1.8 i out2 p1, p2, p5, p6, p7 ports 3.2 output current (per 1 pin) i out3 p3 ports 30 i out2 p1, p2, p5, p6, p7 ports 60 output current (total) i out3 p3 ports 80 ma power dissipation [topr = 85c] pd 350 mw soldering temperature (time) tsld 260 (10 s) storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
tmp86fm29 2004-03-01 86fm29-175 recommended operating condition-1 (mcu mode) (v ss = 0 v, topr = ? 40 to 85c) parameter symbol pins condition min max unit normal1, 2 mode fc = 16 mhz idle0, 1, 2 mode 2.7 normal1, 2 mode fc = 8 mhz (in case of connecting the resonator) idle0, 1, 2 mode normal1, 2 mode fc = 4.2 mhz (in case of external clock input) idle0, 1, 2 mode 1.8 slow1, 2 mode fs = 32.768 khz sleep0, 1, 2 mode supply voltage v dd stop mode 1.8 3.6 v ih1 except hysteresis input v dd 0.70 v ih2 hysteresis input v dd 2.7 v v dd 0.75 input high level v ih3 v dd < 2.7 v v dd 0.90 v dd v il1 except hysteresis input v dd 0.30 v il2 hysteresis input v dd 2.7 v v dd 0.25 input low level v il3 v dd < 2.7 v 0 v dd 0.10 v v dd = 1.8 to 3.6 v 8.0 fc xin, xout v dd = 2.7 to 3.6 v 1.0 16.0 mhz clock frequency (in case of connecting the resonator) fs xtin, xtout v dd = 1.8 to 3.6 v 30.0 34.0 khz v dd = 1.8 to 3.6 v 4.2 fc xin, xout v dd = 2.7 to 3.6 v 1.0 16.0 mhz clock frequency (in case of external clock input) fs xtin, xtout v dd = 1.8 to 3.6 v 30.0 34.0 khz lcd reference voltage v1 booster circuit is enable (v3 v dd ) 0.8 1.2 v capacity for lcd booster circuit c lcd lcd booster circuit is enable (v3 v dd ) 0.1 0.47 f note: the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which incl ude this device, ensure that the recommended operating conditions for the device are always adhered to. recommended operating condition-2 (serial prom mode) (v ss = 0 v, topr = 25c 5c) parameter symbol pins condition min max unit supply voltage vdd 2 mhz fc 16 mhz 2.7 3.6 v clock frequency fc xin, xout vdd = 2.7 to 3.6 v 2.0 16.0 mhz note: the operating temperature area of serial prom mode is 25c 5c and the operating area of high frequency of serial prom mode is different from mcu mode.
tmp86fm29 2004-03-01 86fm29-176 dc characteristics (v ss = 0 v, topr = ? 40 to 85c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 3.3 v ? 0.4 ? v i in1 test v dd = 3.6 v, v in = 0 v ? ? ? 5 i in2 sink open drain, tri-state v dd = 3.6 v, v in = 3.6 v/0 v ? ? 5 input current i in3 reset v dd = 3.6 v, v in = 3.6 v ? ? + 5 a r in1 test pull down v dd = 3.6 v, v in = 3.6 v ? 70 ? input resistance r in2 reset pull up v dd = 3.6 v, v in = 0 v 100 220 450 k ? high frequency feedback resistor r fb xout v dd = 3.6 v ? 3 ? low frequency feedback resistor r fbt xtout v dd = 3.6 v ? 20 ? m ? output leakage current i lo sink open drain, tri-state v dd = 3.6 v v out = 3.4v/0.2 v ? ? 10 a output high voltage v oh cmos, tri-state v dd = 3.6 v, l oh = ? 0.6 ma 3.2 ? ? output low voltage v ol except xout, p3 port v dd = 3.6 v, i ol = 0.9 ma ? ? 0.4 v output low current i ol p3 port v dd = 3.6 v, v ol = 1.0 v ? 6 ? ma v2 pin ? v1 x 2 ? lcd output voltage (lcd booster is enable) v 2-3out v3 pin v3 v dd reference supply pin: v1 seg/com pin: no load ? v1 x 3 ? v flash area mnp = ?1? ? 5.3 7.3 supply current in normal 1, 2 mode fetch area ram area mnp = ?0? ? 3.4 5.2 mnp?atp = ?1? ? 3.1 5.2 supply current in idle 0, 1, 2 mode v dd = 3.6 v v in = 3.4 v/0.2 v fc = 16 mhz fs = 32.768 khz mnp?atp = ?0? ? 2.2 4.2 ma flash area mnp = ?1? ? 850 1200 supply current in slow 1 mode fetch area ram area mnp = ?0? ? 7 19 mnp?atp = ?1? ? 850 1200 supply current in sleep 1 mode mnp?atp = ?0? ? 5.5 17 mnp?atp = ?1? ? 850 1200 supply current in sleep 0 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz mnp?atp = ?0? ? 4.5 15 supply current in stop mode v dd = 3.6 v v in = 3.4 v/0.2 v ? 0.5 10 a note 1: typical values show those at topr = 25c. note 2: input current (i in1 , i in2 ): the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. note 4: the supply currents of slow2 and sleep2 modes are equivalent to idle0, idle1, idle2. note 5: mnp (mnpwdw) shows bit0 in eepcr register and atp (atpwdw) shows bit1 in eepcr register. note 6: ?fetch? means reading operation of flash data as an instruction by cpu.
tmp86fm29 2004-03-01 86fm29-177 ad conversion characteristics (v ss = 0.0 v, 2.7 v v dd 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 3.6 v v ss = 0.0 v ? 0.35 0.61 ma non linearity error ? ? 2 zero point error ? ? 2 full scale error ? ? 2 total error v dd = a vdd = 2.7 v v ss = 0.0 v v aref = 2.7 v ? ? 2 lsb (v ss = 0.0 v, 2.0 v v dd < 2.7 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 0.6 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.0 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 2.0v v ss = 0.0 v ? 0.20 0.34 ma non linearity error ? ? 4 zero point error ? ? 4 full scale error ? ? 4 total error v dd = a vdd = 2.0 v v ss = 0.0 v v aref = 2.0 v ? ? 4 lsb (v ss = 0.0 v, 1.8 v v dd < 2.0 v, topr = ? 10 to 85c) (note 5) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 0.1 ? a vdd power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 1.8 ? ? analog input voltage v ain v ss ? v aref v power supply current of analog reference voltage i ref v dd = a vdd = v aref = 1.8 v v ss = 0.0 v ? 0.18 0.31 ma non linearity error ? ? 4 zero point error ? ? 4 full scale error ? ? 4 total error v dd = a vdd = 1.8 v v ss = 0.0 v v aref = 1.8 v ? ? 4 lsb note 1: the total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to ?2.15.2 register configration?. note 3: please use input voltage to ain input pin in limit of varef ? vss. when voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range: ? varef = varef ? vss note 5: when ad is used with vdd < 2.0 v, the guaranteed temperature range varies with the operating voltage. note 6: when ad converter is not used, fix the avdd pin and varefpin on the v dd level.
tmp86fm29 2004-03-01 86fm29-178 ac characteristics (v ss = 0 v, v dd = 2.7 to 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit normal1, 2 mode idle1, 2 mode 0.25 ? 4 slow1, 2 mode machine cycle time tcy sleep1, 2 mode 117.6 ? 133.3 s high level clock pulse width twch low level clock pulse width twcl for external clock operation (xin input), fc = 16 mhz ? 31.25 ? ns high level clock pulse width twch low level clock pulse width twcl for external clock operation (xtin input), fs = 32.768 khz ? 15.26 ? s (v ss = 0 v, v dd = 1.8 to 3.6 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit normal1, 2 mode idle1, 2 mode 0.5 ? 4 slow1, 2 mode machine cycle time tcy sleep1, 2 mode 117.6 ? 133.3 s high level clock pulse width twch low level clock pulse width twcl for external clock operation (xin input), fc = 4.2 mhz ? 119.04 ? ns high level clock pulse width twch low level clock pulse width twcl for external clock operation (xtin input), fs = 32.768 khz ? 15.26 ? s timer counter 1 input (ecin) characteristics (v ss = 0 v, topr = -40 to 85c) parameter symbol condition min typ. max unit single edge count frequency measurement mode v dd = 2.7 to 3.6 v both edge count ? ? 16 single edge count tc1 input (ecin input) t tc1 frequency measurement mode v dd = 1.8 to 2.7 v both edge count ? ? 8 mhz flash characteristics (v ss = 0 v) parameter condition min typ. max unit number of guaranteed writes (page writing) to flash memory in serial prom mode v dd = 2.7 to 3.6 v, 2 mhz fc 16 mhz (topr = 25c 5c) ? ? 10 5 times recommended oscillating conditions note 1: an electrical shield by metal shield plate on the surface of ic package is recommended in order to protect the device from the high electric field stress applied from crt (cathodic ray tube) for continuous reliable operation. note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following http://www.murata.co.jp/search/index.html

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